الفصل الدراسي الاول

❶

Timing Circuits

Text Book- Chapter 7

12 Hours

1.1 Multivibrator

1.1.1 Monostable Multivibrator Circuits

Simple NAND Gate Monostable Circuit

NOT Gate Monostable Multivibrator

NOR Gate Monostable Multivibrator

Monostable Multivibrator circuit using Transistors

1.1.2 Astable Multivibrator Circuits

NAND Gate Astable Multivibrator

Astable multivibrator using NPN transistors

Switching Times and Frequency of Oscillation

1.1.3 Bistable Multivibrator Circuits

Schmitt Trigger

1.2 The IC 555 Timer

1.2.1 Monostable Operation

1.2.2 Astable Operation

❷

Integrated Circuits Technologies

Text Book- Chapter 15

18 Hours

2.1 Fixed-Function Logic Gates

2.2 Basic Operational Characteristics and Parameters

2.2.1 DC Supply Voltage

2.2.2 Logic Levels

2.2.3 Noise Immunity

2.2.4 Noise Margin

2.2.5 Power Dissipation

2.2.6 Propagation Delay Time

2.2.7 Speed-Power Product (SPP)

2.2.8 Loading and Fan-Out

CMOS Loading

TTL Loading

2.3 CMOS Circuits

2.3.1 The MOSFET

2.3.2 CMOS Inverter

2.3.3 CMOS NAND Gate

2.3.4 CMOS NOR Gate

2.3.5 Open-Drain Gates

2.3.6 Tri-state CMOS Gates

2.3.7 Implementing Logic in CMOS

2.4 TTL (Bipolar) Circuits

2.4.1 The Bipolar Junction Transistor

2.4.2 TTL Inverter

2.4.3 TTL NAND Gate

2.4.4 Open-Collector Gates

2.4.5 Tri-state TTL Gates

2.4.6 Schottky TTL

2.5 Practical Considerations in the Use of TTL

2.5.1 Current Sinking and Current Sourcing

2.5.2 Using Open-Collector Gates for Wired-AND Operation

Pull-up Resistor

2.5.3 Connection of Totem-Pole Outputs

2.5.4 Open-Collector Buffer/Drivers

2.5.5 Unused TTL Inputs

Tied-Together Inputs

Inputs to VCC or Ground

Inputs to Unused Output

2.6 Emitter-Coupled Logic (ECL) Circuits

2.7 PMOS, NMOS, and E^2CMOS

2.7.1 PMOS

2.7.2 NMOS

2.7.3 CMOS

❸

Sequential Circuits

Text Book- Chapter 9

15 Hours

3.1 Finite State Machines

2.1.1 General Models of Finite State Machines

3.2 Asynchronous Counters

3.2.1 A 2-Bit Asynchronous Binary Counter

The Timing Diagram

A 3-Bit Asynchronous Binary Counter

Propagation Delay

3.2.2 Asynchronous Decade Counters

Partial Decoding

3.3 Synchronous Counters

3.3.1 A 2-Bit Synchronous Binary Counter

3.3.2 A 3-Bit Synchronous Binary Counter

3.3.3 A 4-Bit Synchronous Binary Counter

3.3.4 A 4-Bit Synchronous Decade Counter

3.4 Up/Down Synchronous Counters

3.5 Design of Synchronous Counters

3.6 Cascaded Counters

3.7 Counter Decoding

3.8 Counter Applications

3.8.1 A Digital Clock

3.8.2 Automobile Parking Control

3.8.3 Parallel-to-Serial Data Conversion (Multiplexing)

❹

Signal Conversion and Processing

Text Book- Chapter 12

15 Hours

4.1 Analog-to-Digital Conversion

4.1.1 Sampling and Filtering

The Sampling Theorem

The Need for Filtering

Aliasing Concept Illustration

4.1.2 Holding the Sampled Value

4.1.3 Analog-to-Digital Conversion

Quantization Process

4.2 Methods of Analog-to-Digital Conversion

4.2.1 Flash ADC

4.2.2 Dual-Slope ADC

4.2.3 Successive-Approximation ADC

4.2.4 Segma-Delta ADC

4.2.5 Testing Analog-to-Digital Converters

4.2.6 Analog-to-Digital Conversion Errors

Missing Code

Incorrect Code

Offset

4.3 Methods of Digital-to-Analog Conversion

4.3.1 Binary-Weighted-Input DAC

4.3.2 R/2R Ladder DAC

4.3.3 Performance Characteristics of DACs

Resolution

Accuracy

Linearity

Monotonicity

Settling time

4.3.4 Digital-to-Analog Conversion Errors

Nonmonotonicity

Differential Nonlinearity

Low or High Gain

Offset Error

4.3.5 The Reconstruction Filter

❺

Digital Storage Devices

Text Book- Chapter 11

15 Hours

5.1 Semiconductor Memory Basics

5.1.1 Basic Memory Operations

5.2 The Random-Access Memory (RAM)

5.2.1 Static RAMs (SRAMs)

5.2.2 Basic Asynchronous SRAM Organization

5.2.3 Synchronous SRAM with Burst Feature

5.2.4 Cache Memory

5.2.5 Dynamic RAM (DRAM) Memory Cells

5.2.6 DRAM Organization

Address Multiplexing

Fast Page Mode

Refresh Cycles

5.2.7 Types of DRAMs

FPM DRAM

EDO DRAM

BEDO DRAM

SDRAM

DDR SDRAM

5.3 The Read-Only Memory (ROM)

5.3.1 The Mask ROM

5.3.2 Internal ROM Organization

5.3.3 ROM Access Time

5.4 Programmable ROM

5.4.1 PROM

5.4.2 EPROM

5.5 The Flash Memory

5.5.1 Flash Memory Cell

5.5.2 Flash Memory Array

❻

Programmable Logic Devices

Text Book- Chapter 10

15 Hours

6.1 Simple Programmable Logic Devices (SPLDs)

6.1.1 SPLD: The PAL

6.1.2 SPLD: The GAL

6.1.3 Simplified Notation for PAL/GAL Diagrams

6.1.4 Macrocells

6.2 Complex Programmable Logic Devices (CPLDs)

6.2.1 Classic CPLD Architecture

Shared Expanders

Parallel Expanders

6.2.2 LUT CPLD Architecture

6.2.3 PLA (Programmable Logic Array)

6.3 Macrocell Modes

6.3.1 The Combinational Mode

6.3.2 The Registered Mode

6.4 Field-Programmable Gate Arrays (FPGAs)

6.4.1 Configurable Logic Blocks

6.4.2 SRAM-Based FPGAs

6.4.3 FPGA Cores